The present specification relates to the fabrication of integrated circuits (ICs). More specifically, the present specification relates to a patterning process for forming small integrated circuit features.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of devices on an IC, there is still a need to decrease the size of IC device features, and thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The radiation can be light, such as ultra-violet light, vacuum ultra-violet (VUV) light and deep ultraviolet light. The radiation can also be x-ray radiation, e-beam radiation, etc.
The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Exposure of the lithographic coating through a photomask or reticle causes the image area to become selectively crosslinked and consequently either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble (i.e., uncrosslinked) or unprotected areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The photoresist material or layer associated with conventional lithographic technologies is often utilized to selectively form various IC structures, regions, and layers. Generally, the patterned photoresist material can be utilized to define doping regions, implant regions or other structures associated with an integrated circuit (IC). For example, a conventional lithographic system is generally utilized to pattern photoresist material to form gate stacks and other structures. Heretofore, patterning resolution and accuracy have been limited to the dimensions associated with conventional lithography.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need for a process of patterning photoresist material that can achieve smaller dimensions. Yet further, there is a need for a hybrid top surface imaging/isotropic etch process. Even further still, there is a need for gate stacks having smaller widths (smaller gate lengths for the transistor).
An exemplary embodiment relates to a method of fabricating an integrated circuit on a substrate. The method includes providing a photoresist layer above the substrate, patterning the photoresist layer to form a first feature and carbonizing the photoresist layer. The method further includes isotropically etching the photoresist layer and removing the carbonized portion of the photoresist layer to leave a second feature having a width smaller than the first feature.
Another exemplary embodiment relates to a method of fabricating an etch mask for an integrated circuit. The method includes providing a resist layer directly over the layer or substrate to be etched, patterning the resist layer to form a first feature, carbonizing the resist layer to form a carbonized region in the resist layer, and removing portions of the resist layer. The portions of the resist layer are disposed underneath the carbonized region. Removing portions of the resist layer under the carbonized region forms a second feature below the carbonized region. The second feature has a width smaller than the first feature.
Yet another exemplary embodiment relates to a method of forming a gate conductor for an integrated circuit. The method includes steps of providing a photoresist layer above a gate conductor, patterning the photoresist layer to form a first feature, carbonizing a top surface of the photoresist layer, and selectively removing the photoresist layer. The photoresist layer is selectively removed to form a second feature smaller than the first feature. The method also includes etching the gate conductor layer in accordance with the second feature.